Description

Astera Labs is seeking a CAD Engineer with at least 3 years of experience in chip physical design for a Staff/Principal position in our new R&D center in Israel. The role includes developing and maintaining CAD flows and automation for advanced implementation stages, working with tools such as Synopsys Fusion Compiler, and supporting timing and QoR analysis. Strong command of physical design concepts is required, along with experience in Scripting (Tcl, Python), and the ability to work with multiple teams in a complex environment. High interest in integrating GenAI technologies into chip design processes is also desired. Location: Tel Aviv · Department: ASIC Engineering To apply: On the company website, via the button below

Details

Location

Tel Aviv