Staff/ Principal Design Verification Engineer
Description
Design Verification Engineer at Staff or Principal level at Astera Labs, which develops cutting-edge semiconductor connectivity solutions for large-scale AI infrastructure. Your role will be to develop and maintain complex verification environments using SystemVerilog and UVM, including testbenches and test suites for verifying digital blocks and full chip integration, and work in close collaboration with design engineers to identify and resolve complex bugs. Required: Bachelor's degree in Electrical Engineering and 5+ years of proven experience in ASIC verification, with deep knowledge of standard verification methodologies and excellent debugging capabilities. Location: Tel Aviv · Department: ASIC Engineering To apply: On the company website, via the button below
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Location
Tel Aviv
Staff/ Principal Design Verification Engineer
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