Description

Astera Labs is investing in an R&D center in Israel for developing advanced chips that solve connectivity challenges in AI infrastructure at a global scale. We are seeking an ASIC Design Engineer at Staff or Principal level to lead the design of complex digital blocks from initial specification through RTL to implementation stages. The position requires 5+ years of experience in logic design at semiconductor companies, proficiency in Verilog/SystemVerilog, and deep understanding of digital design principles and tools for timing and power consumption analysis. A Master's degree, knowledge of DDR and PCIe protocols, and experience with high-speed serial interfaces would be a significant advantage. Location: Tel Aviv · Department: Design Engineering CCE2 To apply: Visit the company website using the button below

Details

Location

Tel Aviv