Senior/Staff Formal Verification Engineer
Description
Senior Formal Verification Engineer at Astera Labs in the Silicon Engineering department, responsible for developing and managing formal verification environments from initial stages through final design sign-off for chips connected to AI infrastructure worldwide. The position requires 4+ years of experience in Formal Verification at semiconductor companies with deep proficiency in tools such as Jasper and VC Formal, comprehensive understanding of RTL design and design rules, and strong communication skills. Advantage for candidates with experience in SystemVerilog UVM and knowledge of Ethernet, NVLink, or PCIe standards. Location: Tel Aviv · Department: Silicon Engineering CCE2 To apply: On the company website, via the button below
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Location
Tel Aviv
Senior/Staff Formal Verification Engineer
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