Senior Design Verification Engineer
Description
Design Verification Engineer (Senior) at Astera Labs. Position in developing complex verification environments for next-generation ASIC chips for AI infrastructure. The role includes developing testbenches and SystemVerilog/UVM environments, coverage analysis, and debugging of complex digital blocks in collaboration with the Design team. Required: Bachelor's degree in Electrical Engineering, 3+ years of experience in ASIC verification, deep knowledge of SystemVerilog and standard verification methodologies, primarily UVM. Preferred: Master's degree, experience with protocols such as PCIe or CXL, and strong debugging and analytical thinking skills. Location: Tel Aviv · Department: ASIC Engineering To apply: On the company website, via the button below
Details
Location
false
Location
Tel Aviv
Senior Design Verification Engineer
This role is published on Astera Labs's own site. You apply there; our part is getting it seen.
Apply on the company siteAsk about this listingSource
This listing was collected from a public external source. To contact the poster, visit the original post.
Original page at job-boards.greenhouse.io