Manager Design Verification
Description
Manager Design Verification at Astera Labs will lead the execution of RTL design in complex blocks within the CCE2 connectivity platform, working on PCIe, CXL, Ethernet technologies and innovative interfaces for AI infrastructure. The role requires 5+ years of experience in digital design with strong command of Verilog/SystemVerilog, timing closure and CDC, alongside deep understanding of high-speed interfaces. As a manager you will be responsible for collaboration with Architecture, Verification and Physical Design teams, managing the design cycle from design through tapeout, and mentoring junior engineers. A high-impact technical role in a fast-growing company, on a mission to deliver silicon that defines global AI infrastructure. Location: Tel Aviv · Department: Design Verification CCE2 To apply: On the company website, via the button below
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Location
Tel Aviv
Manager Design Verification
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