Senior Design Verification Engineer
Description
A Senior Design Verification Engineer at Astera Labs will develop advanced verification environments for ASIC chips intended for AI infrastructure worldwide. The role includes developing testbenches at unit and sub-system levels using SystemVerilog and UVM, executing detailed verification plans, and implementing functional coverage models. The candidate will work closely with design engineers to identify and implement fixes in complex digital designs. Required: a bachelor's degree in electrical engineering or a related field, knowledge of digital logic, proficiency in programming (C/C++ or Python), and basic familiarity with Verilog or SystemVerilog. Location: Tel Aviv · Department: ASIC Engineering To apply: On the company website, via the button below
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Location
Tel Aviv
Senior Design Verification Engineer
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